A memory system is coherent if the value read by a data read or instruction fetch is always the value that was most recently written to that location. Memory coherency is difficult when the memory system includes multiple possible physical locations, such as main memory and at least one of a write buffer or one or more caches (ARM glossary, www.arm.com).
There are various prior art cache coherent interconnect that provide full cache coherency between clusters of multi-core processors (CPUs) and input/output (I/O) coherency for devices such as I/O masters and the like.
Various system on chip architectures are tailored to applications such as mobile applications (especially smart phones) where the throughout and bandwidth are relatively small.
Such architectures may have various drawbacks. Some of these drawbacks include:    a. A cache coherent interconnect may be connected to a dynamic random access memory (DRAM) module. Accessing to the DRAM module is time consuming and the ARM architecture is characterized by inefficient DRAM accesses.    b. A cache coherent interconnect may prevent pipelining of transactions requests that have a same transaction identifier. Thus, when multiple transaction requests that have a same transaction identifier are received by the cache coherent interconnect—the cache coherent interconnect will service only one transaction request at a time—and this can introduce vary large delays.    c. Write operations of portions of a cache line require multiple DRAM read and write operations.
There is a growing need to provide method and systems for enhancing the capability of interconnects